Parent: Processor Architectures

Intel and AMD Historical, Pentium 4, AMD Opteron, Dual Core, Pentium M to Core 2, Nehalem, Sandy Bridge to Haswell, Hyper-Threading, SIMD Extensions

Pentium M and Core Interlude

The Intel Pentium 4 architecture was designed to be a mainstream desktop processor with server and mobile versions. The goal was best performance within the desktop platform cost structure, including a reasonable power and thermal envelop for desktop systems. It was realized early in the design phase that the performance-power efficiency of the Pentium 4 was too high to be suitable for the mobile platform.

Chopaka and Timna

Initially, another architecture group was tasked to design a microprocessor described as an improved P6 microarchitecture with the codename Chopaka. This project was cancelled mid-stream with the new task to build as quickly as possible an integrated processor with the codename Timna. Time to market was deemed so critical that this was to be the existing Pentium III, north bridge (memory controller) and graphics all bolted on to a single-die, even retaining a front-side bus between the processor and memory controller. Had the normal four year development cycle been available, the memory controller would have been integrated into the microprocessor with reduced latency and better performance.

Unfortunately for Intel, the memory controller hub available was for Rambus memory. A Rambus to SDRAM Memory Translator Hub was also built as this was intended to target the low cost segment. After the Timna design was complete, and pre-production samples were sent out, most system vendors came to the conclusion that the Timna product line did not match up with any market segements. (cancelled Sep 2000) In other words, enough cost had already been extracted out the mainstream Pentium III system, that a crippled version was not necessary. A corollary might have been the IBM PC junior.

Pentium M

The design group then reverted to a microprocessor optimized for performance and power efficiency suitable for the mobile market. The first product had the codename Banias on 130nm in Mar 2003 (see The Intel® Pentium® M Processor: Microarchitecture and Performance).

Banias
Banias, 2003, 130nm, 83mm2, 1M L2

This became Pentium M and was targeted only at mobile platforms. One might think that this would the previously cancelled Chopaka, but the Intel Technology Journal described Banias as a clean sheet design, instead of a significantly improved Pentium III architecture. The paternity/maternity of Pentium M will not be discussed here. The Pentium M performance characteristics were appropriate to be considered one full generation improvement over Pentium III also at 130nm (Tualatin).

The 90nm version of Pentium M in Jun 2004 Q2 had the codename Dothan (see Performance and Power Consumption for Mobile Platform Components Under Common Usage Models).

Dothan
Dothan, 2004?, 90nm, 84mm2, 2M L2

Yonah, first called Core Duo, then Pentium

The next design from this group was codename Yonah (see Introduction to Intel® Core™ Duo processor architecture, pdf) on 90nm in 2006 Q1, a dual-core improved Pentium M design. The brand name for Yonah became Core instead of Pentium M. The Intel Core Duo was a dual-core processor, with a single-core variant called Core Solo. The product name later reverted to Pentium. Note that the Pentium M and Core were 32-bit microprocessors as were the Pentium III.

Dothan
Yonah, 2006, 65nm, 90mm2, 2×1M L2

Even Pentium M and Core (later Pentium) were all designed with objectives balanced between performance and the more restrictive mobile platform power and thermal envelop, the performance was still respectable compared with contemporary desktop processors with less restrictive power constraints.

Core 2 (65nm)

Having established credibility in designing microprocessors with both performance and power efficiency, the next product from this group was a new 64-bit dual-core architecture on the 65nm process with the codename Conroe for desktop and Merom for mobile segments. The initial public name was Core 2 in the desktop and mobile markets. Core 2, which is now rebranded Core, with the original Core being rebranded Pentium. (Presumably extra marketing staff was added to handle all the powerpoint slides that had to be changed for this.)

The rapid turn from Banias (Mar 2003), to Yonah (Jan 2006) and Conroe (Jul 2006) was truely impressive considering that each represented a significant improvement at the core level over its predecessor.

Nehalem

See the wikipedia page on Core microarchitecture.

Core 2

With Core 2, Intel discarded the previous practice of having one large design group for desktop processors plus variant, and another large group for mobile processors. The new organization established the tick-tock method with each team producing and new microarchitecture every four years, allowing a new architecture to be introduced every two years, and having a process shrink with minor improvements for the in-between years. Intel roadmaps show the tock processors in the even years, and tick processors in the odd years. However, the actual target launch dates tend to be towards the end of the year, and if an extra stepping is required, may drift to the next year.

The Core 2 on 65nm, has two cores, with 4M L2 shared cache, and run at up to 3.0GHz.

In the server market, the dual-core Core 2 became the Xeon 5100 series for 2-way systems (Jun 2006). There was also a dual-core Core 2 for single socket servers as the Xeon 3000 series. Later, a dual-die quad-core version became the Xeon 5300 series (Jan 2007). The dual-die quad-core codename Tigerton became the Xeon 7300 series in Sep 2007.

Conroe Conroe

Xeon 7300 (2 Conroe die), 65nm, 143mm2, dual core per die, 65nm, 4M L2, 291M (2007)

The Core 2 architecture at 3GHz was far more powerful that the Pentium 4 architecture at 3.4GHz or Opteron at 2.8GHz at the processor core level. This is evidenced by the SPEC CPU Integer base scores of 21 for Core 2, 12 for the Pentium 4, and 13 for Opteron. Single query tests in SQL also demonstrate the outstanding single-core performance of the Core 2 architecture.

Core 2 (45nm)

The 45nm Core 2, codename Penryn was also a dual-core with the shared L2 cache increased from 4M in Conroe to 6M (107mm2 die size). (see Improvements in the Intel® Core™2 Penryn Processor Family Architecture and Microarchitecture).

Penryn
Penryn, 2007 Nov, 45nm, 107mm2, 6M L2

There was also a Penryn with 3M L2.

Penryn
Penryn, 2007 Nov, 45nm, 81mm2, 3M L2

For 2-way servers, the single-die dual-core 45nm Core 2 product was the Xeon 5200 series (Feb 2008) and the two-die quad-core was the Xeon 5400 series (2007 or Mar 2008?).

Note: In the beginning, the Xeon brand meant 4-way+ systems for server platforms, even though there were 2-way workstations. The 2-way servers used standard desktop Pentium II or III processors. With Pentium 4, desktop processors were now only for single-socket platforms. Xeon became the brand for 2-way servers. Xeon MP was the brand for 4-way and higher, even though the Xeon processor of this time were really not meant to scale well. Then in 2006, Xeon 7000 was used for 4-way and higher, Xeon 5000 for 2-way, and Xeon 3000 for single socket servers.

During this time, a procesor architecture had different codenames for each market segment. Eventually, people got tired of this sillyness, and there was a single codename, with the suffix EP denoting Enhanced Performance for 2-way servers, and the EX denoting Expandable Perfomance for 4-way and higher.

By keeping the marketing people busy with unending powerpoint alterations, they do not have time to make other contributions to the design effort?

For 4-way+, there was a special variant with six cores integrated into a single die with 16M L3 cache and 1.9 billion transistors, codename Dunnington, officially the Xeon 7400 series (Sep 2008). Each of the three dual-core sets had its own 3M L2 cache shared between the two cores. Below is the Dunnington die, shown next to Penryn. The 2 sections labeled cache is the L3 cache. The other part that looks like cache but not labeled is the L2 cache.

Dunnington Penryn Dunnington

Xeon 7400, 45nm, 503mm2, 3 dual core pairs, 3 x 3M L2, 16M L3