Systems Architecture - Parent
Historical,
AMD Opteron,
Intel QPI,
Dell PowerEdge,
HP ProLiant,
IBM x Series,
NUMA,
Sandy Bridge,
Intel Sandy Bridge based systems with QPI 1.1
Sandy Bridge is a new micro-architecture suceeding the Nehalem architecture, but sharing the same 32nm process as Westmere, per Intel's Tick-Tock strategy. There are several versions of Sandy-Bridge, including two dual-core versions differing in the on-die graphics having 6 or 12 execution units. There is also a quad-core version without on-die graphics. These three versions are currently available for single socket systems. Later (2012 Q1 perhaps) there will be the Sandy Bridge EN for entry 2-socket systems and Sandy Bridge EP for high-end 2-socket and 4 socket systems. There will not be an EX version capable of support glue-less 8-way until the Ivy Bridge generation(?)
The only Sandy Bridge products currently available are the dual and quad core models without QPI. Some models have integrated graphics and others do not. There 16 PCI-E gen 2 lanes plus DMI 2, which is essentially a PCI-E gen 2 x4 port with additional capabilities to support legacy functions. The server variant is the Xeon E3 series.
Coming in early 2012(?) are the EN and EP versions, both with up to 8 cores per socket. The EN has 3 memory channels, 1 QPI, 24 PCI-E (gen 3?) lanes and DMI 2. The EP has 4 memory channels, 2 QPI, 40 PCI-E and DMI 2. It might the intent for EN to support 2-socket systems at moderately lower cost structure than Nehalem/Westmere-EP, in not having the IOH?
The Sandy Bridge EP fits in above the current EP but somewhat below the EX in not supporting glue-less 8-way systems,
fewer cores (8 versus 10 in Westmere-EX) , and 8 DIMMs per socket versus 16?.
The 2-way system below shows memory connected directly to the processor.
In this case the memory channel signalling rate would follow the current Nehalem/Westmere-EP pattern of 1333MHz with 1 DIMM per channel,
1066 for 2 and 800 for 3.
Presumably the SMB, which expands a single memory channel into 2 could support 4 DIMMs at 1066MHz similar to the Nehalem/Westmere-EX systems, Sandy Bridge EP could suceeds both the Westmere-EP platforms with 2 IOH, and the 2-socket high-memory EX systems. There is no particular reason either system could be configured with or without the SMB. With 8 DIMMs per socket and 16GB DIMMs, this is 128GB per socket, or 256GB per socket with 16 DIMMs each. There is currently a price premium for a 16GB DIMM over 2 8GB DIMMs, but this should close over the next year as the 32GB DIMM becomes the premium part.
DDR3 note: 8 internal banks. 1066MHz DDR has 8 x 133MHz internal banks? Two transfers per cycle of quadrupled clock. Transfer rate is memory clock x 4 (bus multiplier) x 2 (data rate). 8-burst deep prefetch buffer.
Wikipedia provides the information below:
- 32 kB data + 32 kB instruction L1 cache (3 clocks)
- and 256 kB L2 cache (8 clocks) per core
- Shared L3 cache includes the processor graphics (LGA 1155)
- 64-byte cache line size
- Two load/store operations per cycle for each memory channel
Decoded micro-op cache and enlarged, optimized branch predictor
Improved performance for transcendental mathematics, AES encryption, and SHA-1 hashing
256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain
Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax, and rich functionality
Intel Quick Sync Video, hardware support for video encoding and decoding
Up to 8 physical cores and 16 logical cores through Hyper-threading, in selected models.
Ivy Bridge is the codename for the yet-to-be released 22 nm die shrink of Sandy Bridge.
Ivy Bridge processors will be backwards-compatible with the Sandy Bridge platform.
Ivy Bridge processors are expected in March-April 2012.
Expected Ivy Bridge feature improvements from Sandy Bridge:
Intel's tri-gate transistor technology, which will significantly reduce power consumption.
PCI Express 3.0 support.
Next Generation Intel HD Graphics with DirectX 11, OpenGL 3.1, and OpenCL 1.1 support.
The built-in GPU is believed to have up to 16 execution units (EUs), compared to Sandy Bridge's maximum of 12.
Next Generation Intel Quick Sync Video.
The new random number generator and the RdRand instruction, which is codenamed Bull Mountain.
While Ivy Bridge will be compatible with the Cougar Point chipset motherboards associated with Sandy Bridge,
Intel will also release a new 7-series Panther Point chipset with Ivy Bridge. This chipset will have integrated USB 3.0.
| Socket | Cores | Graphics | Transistor count | Die size |
|---|---|---|---|---|
| LGA 1155 | 4 | ? | 995 Million | 216 mm2 |
| 2 | 6 EUs | 504 Million | 131 mm2 | |
| 2 | 12 EUs | 624 Million | 149 mm2 |
The figure below shows a functional representation on the Sany-Bridge EN/EP die layout (not necessarily the actual layout).
Below is a comparison of common and differentiating features for 2-scoket EN and EP.
More details of the Sandy Bridge EN/EP PCH, codenamed Patsburg. Note the 4 x 6Gbps SAS ports, along with 2 6Gbps and 4 3Gbps SATA ports, PCI-E lanes and other.
In the figure below, note that 2 QPI links connect the sockets of an EP platform.
